Field of the Invention
The present invention relates to a multimaster bus system having a bus for connecting devices that are connected thereto, and having a bus controller that controls the bus and/or the bus allocation.
Multimaster bus systems have been in numerous prior art embodiments for many years. The basic configuration of such a bus system is illustrated in FIG. 1.
The bus system illustrated includes a bus BUS and a bus controller BC. The bus has devices U1, U2, . . . connected to it. These devices U1, U2, . . . are connected to one another through the bus and to the bus controller BC through lines, which are not shown in FIG. 1; the bus controller controls the bus and/or the bus allocation.
The devices U1, U2, . . . can be any electrical or electromechanical device. In the example under consideration, they might be various components of a microcontroller, that is to say, by way of example, its CPU, its internal memory device(s), its A/D converter, its D/A converter, its interrupt controller, its DMA controller, its interfaces to external buses and devices, etc.
The devices U1, U2, . . . can be masters, slaves, or either masters or slaves in the bus system. In the example under consideration, there are a number of devices that can be masters in the bus system (hence, the bus system under consideration in the present case is referred to as a multimaster bus system).
A device that is a master can autonomously transmit data and/or signals to one of the other devices connected to the bus, or can request and receive data and/or signals from one of the other devices connected to the bus. If a device wants to become a master, it generally needs to report this to the bus controller BC (for example, by transferring a “bus request signal” to the bus controller BC). The bus controller checks if the device in question can become a master, and, as soon as this is the case, the bus controller reports the status to the device (for example, by transmitting a “bus grant” signal to the device requesting the master authorization). Such action makes the device in question the master of the bus system for the time being.
The devices that are slaves check whether or not they are being addressed by the data and/or signals transferred through the bus, for example, by an address that is associated with them. In such a case, if a device establishes that it has been addressed, it may then check what it needs to do in this case, and then performs the action that is expected of it. By way of example, the expected action can be that the device in question accepts data sent through the bus or outputs particular data to the bus.
Bus systems of the type shown in FIG. 1 have the drawback that only one of the connected devices U1, U2, . . . can ever be a master at one time. This means that the bus can only ever be used to transfer data and/or signals between one master and a slave. Such is frequently a drawback, particularly, in cases in which a plurality of the devices connected to the bus can be masters.
Bus systems in which a plurality of the devices connected to the bus are simultaneously able to be masters and to interchange data and/or signals with various slaves are in the prior art. Such a system can be produced, by way of example, by a network of connections that connects each of the devices connected to it to all the other devices using separate lines. Such systems are called fully interconnected networks. However, the practical implementation of such and similar systems is associated with a very high level of complexity, particularly, due to the many long lines that need to be provided between the devices.